1. Field of the Invention
The present invention relates to a semiconductor memory device having a semiconductor memory circuit, a semiconductor test circuit, a semiconductor circuit other than the semiconductor memory circuit and the semiconductor test circuit, and a plurality of pads against which probes are respectively pressed upon testing the semiconductor memory circuits and to which wires for connecting lead terminals are respectively electrically connected upon packaging, all of which are provided on the same substrate.
2. Description of the Prior Art
FIG. 10 is a plan view showing a configuration of a conventional semiconductor memory device. FIG. 10 illustrates the manner in which a semiconductor memory circuit is being tested while pressing probes against five first pads provided at one of a plurality of semiconductor memory devices formed on a semiconductor wafer, viewed through a window hole defined substantially in the center of a probe card. The plurality of semiconductor memory devices formed on the semiconductor wafer are divided into respective semiconductor memory devices in the subsequent dicing process. In FIG. 10, reference numeral 101 denotes a semiconductor memory circuit including an originally-used first memory circuit 101a and a second memory circuit 101b used in place of the first memory circuit 101a when the first memory circuit 101a fails to function properly. Reference numeral 102 denotes a semiconductor test circuit for testing the semiconductor memory circuit 101. Reference numeral 103 denotes a logical circuit for swapping data with the semiconductor memory circuit 101. Reference numerals 104 respectively denote first pads against which probes are respectively pressed upon testing the semiconductor memory circuit 101 and to which wires for connecting to lead terminals are respectively electrically connected upon packaging. Reference numerals 105 respectively denote second pads that are not in contact with the probes upon testing the semiconductor memory circuit 101 but electrically connected with wires for connecting to lead terminals upon packaging. Reference numeral 106 denotes a substrate provided with the semiconductor memory circuit 101, the semiconductor test circuit 102, the logical circuit 103, and the first and second pads 104 and 105. Further, reference numeral 107 denotes a probe card and reference numerals 108 denote probes attached to the probe card 107. Incidentally, reference numerals 105 are assigned only to parts of the second pads in FIG. 10. For brevity of illustration, the wires electrically connected to the second pads 105 are omitted and not shown in the drawing.
The conventional semiconductor memory device is shaped in the form of a square. The five first pads 104 are divided into groups of two pads, one pad, one and one pad placed along the four sides of the outer periphery of the semiconductor memory device.
The operation of the semiconductor memory device will next be described.
FIGS. 11A through 11C are respectively schematic side views showing the states of first pads 104 and probes 108 at the time that the probes 108 are respectively pressed against the first pads 104 in a test process of the semiconductor memory circuit. FIGS. 12A through 12C are respectively schematic plan views showing the states of the first pads 104 at the time that the probes 108 are respectively pressed against the first pads 104 and thereafter the probes 108 are respectively removed from the first pads 104 in the test process of the semiconductor memory circuit.
When the semiconductor memory circuit is tested, the probes 108 are first respectively pressed against the first pads 104 placed along the four sides of the outer periphery of the semiconductor memory circuit. Next, a test is made as to whether the first memory circuit 101a operates properly. In this case, a first probe contact trace 111 is developed in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11A). Therefore, when the probe 108 is removed from the first pad 104, the first probe contact trace 111 remains in the first pad 104 (see FIG. 12A).
Thereafter, when the first memory circuit 101a fails to operate properly, the first memory circuit 101a is switched to the second memory circuit 101b and the probes 108 are respectively pressed against the first pads 104 disposed along the four sides of the outer periphery again. Next, a test is made as to whether the second memory circuit 101b operates properly. In this case, a second probe contact trace 112 occurs in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11B). Therefore, the second probe contact trace 112 thereafter remains in the first pad 104 when the probe 108 is removed from the first pad 104 (see FIG. 12B).
Thereafter, when the second memory circuit 101b functions properly, the probes 108 are respectively pressed against the first and second pads 104 and 105. Next, a test is made as to whether the entire semiconductor memory device operates properly. In this case, a third probe contact trace 113 is developed in the first pad 104 by pressing the probe 108 against the first pad 104 (see FIG. 11C). Therefore, the third probe contact trace 113 thereafter remains in the first pad 104 when the probe 108 is removed from the first pad 104 (see FIG. 12C).
Since the conventional semiconductor memory device is constructed as described above, a problem arises in that in the test process of the semiconductor memory circuit, the probes 108 must be pressed against the first pads 104 placed along the four sides of the outer periphery thereof from four directions and a plurality of semiconductor memory devices cannot be tested simultaneously upon testing the semiconductor memory circuit.
Further, a problem arises in that since the first through third probe contact traces 111 through 113 remain in the first pads 108 respectively after the test process of the semiconductor memory circuit when the first memory circuit 101a fails to function properly, a wire 114 for connecting to a lead terminal is hard to connect to its corresponding first pad 104 upon packaging as shown in FIGS. 13A and 13B. FIG. 13 is a schematic view showing the state of the first pad 104 and the wire 114 at the time that the wire 114 for connecting to the lead terminal is electrically connected to the first pad 104, in which FIG. 13A is a side view and FIG. 13B is a plan view.